The present disclosure relates to a current type digital-to-analog (D/A) converter and a delta-sigma modulator including such a D/A converter, and particularly relates to a technique for reducing occurrence of harmonic distortion.
It general, it is known that analog-to-digital (A/D) converters for use in delta-sigma modulators achieve, by noise shaping and oversampling techniques, higher precision and lower power dissipation than Nyquist A/D converters do. Among various types of delta-sigma modulators, a continuous-time delta-sigma modulator has been known as a tool suitably used to realize high-speed and broadband operation. In a continuous-time delta-sigma modulator, an input signal passes through a loop filter including a plurality of analog integrators or resonators which are cascaded together, and then is quantized by a quantizer. The digital output thus quantized is converted next into an analog signal by a digital-to-analog (D/A) converter and then fed back (see, for example, Steven R. Norsworthy, Richard Schreier and Gabor C. Temes, “Delta-Sigma Data Converters Theory, Design and Simulation,” (USA), Wiley-IEEE Press, 1997, pp. 1-6, and H. Inose, Y. Yasuda, “A unity bit coding method by negative feedback,” (USA), Proceedings of the IEEE, November 1963, Vol. 51, pp. 1524-1535).
In general, in order to improve the conversion precision of a delta-sigma modulator, a multi-bit quantizer and a multi-bit feedback D/A converter may be used by increasing the number of elements that form the quantizer and the feedback D/A converter. However, when a multi-bit feedback D/A converter is used, some distortion occurs due to a mismatch between the elements of the feedback D/A converter, resulting in a decrease in the conversion precision of the delta-sigma modulator. To address this problem, a dynamic element matching (DEM) circuit has been used to shuffle the elements of a D/A converter to perform D/A conversion. This allows for leveling the mismatch between the elements and eventually reducing the distortion (see, for example, Y. Geerts, M. Steyaert, W. Sansen, “Design of Multi-bit Delta-Sigma A/D Converters,” (USA), Kluwer Academic Publishers, May 2002, pp. 74-97).
When data weighted averaging (DWA) is used as an algorithm for a DEM circuit in a delta-sigma modulator, the D/A converter selected in such a situation has correlation with the input frequency due to the characteristics of the DWA. Harmonic distortion occurs in the output signal of the delta-sigma modulator due to a parasitic capacitance of the feedback D/A converter, and an input offset voltage of an operational amplifier in the loop filter (see, for example, Kazuo Matsukawa, and six other persons, “A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver,” Custom Integrated Circuits Conference (CICC), 2010 IEEE (USA), 19-22 Sep. 2010, pp. 1-4).
U.S. Pat. No. 6,522,277 discloses a bi-directional DWA (Bi-DWA) technique for a DEM circuit in a delta-sigma modulator. According to this technique, two pointers are provided for the DEM circuit, and are alternately moved in two opposite directions, thereby reducing occurrence of harmonic distortion including second-order harmonics.